In a typical synchronous dynamic random-access memory (SDRAM) design, each data byte (8 bits of data) of a ×8 SDRAM device or each nibble (4 bits of data) of a ×4 SDRAM device is associated with a dedicated data strobe (DQS). In a ×4 mode, two DQS signals (e.g., namely DQS0, DQS1) are used to clock one byte, and each DQS is associated with 4 data bits (DQs); whereas, in a ×8 mode, one DQS (e.g., namely DQS0) is associated with all 8 DQ bits in the byte. The ×4 mode thus requires an extra bidirectional data strobe signal, DQS1, to be sent between the memory controller and the memory. DQs and the differential data strobes (DQSs) are transported through bi-directional buses and are driven by the memory controller during a memory write and driven by the memory during a memory read.
A memory controller usually interfaces with more than one DRAM device to form one memory channel. A common clock/command/control/address is daisy-chained across several memory devices. This is commonly known as fly-by topology. Because of the topology, the clock, command, control and address signals arrive at each device at different time. Thus, the data and data strobe between the controller and each device need to be delayed or pre-launched appropriately to account for the fly-by delay such that the write and read latency perceived by each device will be equal, or leveled. This adjustment process for the write path is called “write leveling” while for the read path it is called “read leveling.”
Because the arrival time of the clock, command control and address bus to each device usually is different, the leveling should be done on a per device basis. However, the data width of each device could be different depending on different applications. In the case of ×8 devices being used, for example, all 8 DQ bits and one data bus inversion (DBI) bit to and from each device can be leveled under the same settings. For the case of a ×4 configuration, because there are two devices interfacing with the controller off-chip per byte, there will likely be different insertion delays between them. 4 DQ bits of a ×4 device can be leveled together while another 4 DQ bits within the same byte may need to be leveled differently if two ×4 devices which form the same bytes are having different arrival time on the clock, command, control and address bus.
When the memory controller interfaces with a ×8 device, one set of write and read leveling setting is usually needed per byte. However, when it interfaces with two ×4 devices for a byte, two sets of write and read leveling settings are needed. This adds complexity to the memory controller design.